Please use this identifier to cite or link to this item:
https://ir.vidyasagar.ac.in/jspui/handle/123456789/770| Title: | Design of a Phase Detector with Improved Performance |
| Authors: | Chakraborty, B Pal, R.R |
| Keywords: | Phase Detector (PD) Voltage Controlled Oscillator (VCO) Emitter Coupled Logic (ECL) Phase Locked Loop (PLL) |
| Issue Date: | 2008 |
| Publisher: | Vidyasagar University , Midnapore , West-Bengal , India |
| Series/Report no.: | Journal of Physical Science;Vol 12 [2008] |
| Abstract: | This paper presents a new type of bipolar analog Phase Detector (PD) using a high speed low voltage Emitter Coupled Logic (ECL) inverters, where positive feedback has been introduced to increase the operating range. Introduction of positive feedback has also reduced the supply voltage requirement. The same technique has been introduced in a NMOS Gilbert phase detector and similar results were obtained. The minimum supply voltage required for both these circuits were 2.1 volts. |
| Description: | 213-220 |
| URI: | http://inet.vidyasagar.ac.in:8080/jspui/handle/123456789/770 |
| ISSN: | 0972-8791 (Print) |
| Appears in Collections: | Journal of Physical Sciences Vol.12 [2008] |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| JPS12-19.pdf | 380.7 kB | Adobe PDF | View/Open |
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